HEF4027BT-Q100中文资料Dual JK flip-flop数据手册Nexperia规格书

描述 Description

The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 3)
• Specified from -40°C to +85°C

• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• ESD protection:
• MIL-STD-833, method 3015 exceeds 2000V
• HBM JESD22-A114F exceeds 2000V
• MM JESD22-A115-A exceeds 200 V (C = 200pF, R = 0Ω)

• Complies with JEDEC standard JESD 13-B

应用 Application

• Registers
• Counters
• Control circuits