Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 页数：5 Pages

PHI

飞利浦

Dual JK Flip-Flop

Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independe

文件：48.07 Kbytes 页数：6 Pages

INTEGRAL

Integral Corp.

Dual JK Flip-Flop

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override th

文件：158.11 Kbytes 页数：6 Pages

IKSEMICON

Dual JK Flip-Flop

Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independe

文件：48.07 Kbytes 页数：6 Pages

INTEGRAL

Integral Corp.