Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

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PHI

飞利浦

5V CATV MODEM RF TUNER AND TRANSMITTER

文件：150.24 Kbytes 页数：8 Pages

SIRENZA

5V CATV MODEM RF TUNER AND TRANSMITTER

文件：161.51 Kbytes 页数：8 Pages

SIRENZA

QUAD CLOCKED > LATCH

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferr

文件：154.11 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.