Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：39.77 Kbytes 页数：7 Pages

HitachiHitachi Semiconductor

日立日立公司

Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.31 Kbytes 页数：7 Pages

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Triple 3-input NOR Gates

• High Speed Operation: tpd = 10 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 10 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C) ;

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瑞萨

Triple 3-input NOR Gates

• High Speed Operation: tpd = 10 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 10 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C) ;

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Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

文件：71.48 Kbytes 页数：10 Pages

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Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

文件：56.35 Kbytes 页数：10 Pages

HitachiHitachi Semiconductor

日立日立公司

Quad. S-R Latches

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

文件：59.1 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

日立日立公司

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

文件：179.58 Kbytes 页数：6 Pages

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Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

文件：179.58 Kbytes 页数：6 Pages

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瑞萨

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

文件：179.58 Kbytes 页数：6 Pages

RENESAS

瑞萨