HD74HC279FPEL中文资料瑞萨数据手册PDF规格书

Description

The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but this high level are uncontinuance, if either of input goes high.

Features

• High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)