Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.31 Kbytes 页数：7 Pages

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Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.31 Kbytes 页数：7 Pages

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Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.31 Kbytes 页数：7 Pages

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Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes 页数：10 Pages

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Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes 页数：10 Pages

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Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes 页数：10 Pages

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Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes 页数：10 Pages

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Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes 页数：10 Pages

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SEMICONDUCTORS

文件：2.43533 Mbytes 页数：31 Pages

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Octal D-type Flip-Flops (with Clear)

Description\nThis device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. •  High Speed Operation: tpd(Clock to Q) = 18 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C);

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