Triple 3-input AND Gates

Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.37 Kbytes 页数：7 Pages

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Triple 3-input AND Gates

Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.37 Kbytes 页数：7 Pages

RENESAS

瑞萨

Triple 3-input AND Gates

Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.37 Kbytes 页数：7 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

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Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

RENESAS

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Dual J-K Flip-Flops (with Preset and Clear)

Description\nEach flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic le •  High Speed Operation: tpd(Clock to Q) = 17 ns typ (CL = 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 2 µA max (Ta = 25°C);

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