Dual 4-bit Binary Counters

Description\nEach flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic le •  High Speed Operation: tpd(Clock to Q) = 17 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 2 µA max (Ta = 25°C)\n•  Ordering Information;

Renesas

瑞萨

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

RENESAS

瑞萨

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The IN74HC112A is identical in pinout to the LS/ALS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Each flip-flop is negative-edg

文件：233.67 Kbytes 页数：6 Pages

IKSEMICON

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The IN74HC112A is identical in pinout to the LS/ALS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Each flip-flop is negative-edg

文件：233.67 Kbytes 页数：6 Pages

IKSEMICON