Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：188.83 Kbytes 页数：7 Pages

RENESAS

瑞萨

DUAL J-K FLIP FLOP WITH PRESET

DESCRIPTION The M54/74HC113 is a high speed CMOS DUAL JK FLIP FLOP WITH PRESET fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■

文件：247.82 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

DUAL J-K FLIP-FLOP WITH SET AND RESET

DUAL J-K FLIP-FLOP WITH SET AND RESET

文件：256.029 Kbytes 页数：6 Pages

ETC1List of Unclassifed Manufacturers

etc未分类制造商未分类制造商

Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：52.31 Kbytes 页数：8 Pages

HitachiHitachi Semiconductor

日立日立公司

Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：188.83 Kbytes 页数：7 Pages

RENESAS

瑞萨