3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enab

文件：117.62 Kbytes 页数：10 Pages

RENESAS

瑞萨

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

文件：256.38 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSC

国半

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSC

国半