HD74HC137P

3-to-8-line Decoder/Demultiplexer with Address Latch

Description TheHD74HC137implementsathree-to-eightlinedecoderwithlatchesonthethreeaddressinputs.WhenGLgoesfromlowtohigh,theaddresspresentattheselectinputs(A,BandC)isstoredinthelatches.AslongasGLremainshighnoaddresschangeswillberecognized.Outputenab

74HC137

3-to-8linedecoder/demultiplexerwithaddresslatches;inverting

74HC137

3-to-8linedecoder/demultiplexerwithaddresslatches;inverting

GENERALDESCRIPTION The74HC/HCT137arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •Combines3-to-8decoderwith3-bitlatch •Multipleinputenableforeasyexpansionorind

74HC137

3-to-8linedecoder,demultiplexerwithaddresslatchesinverting

74HC137

3-to-8linedecoder,demultiplexerwithaddresslatches;inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137D

3-to-8linedecoder,demultiplexerwithaddresslatches;inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137D

3-to-8linedecoder,demultiplexerwithaddresslatchesinverting

74HC137DB

3-to-8linedecoder,demultiplexerwithaddresslatchesinverting

74HC137DB

3-to-8linedecoder,demultiplexerwithaddresslatches;inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137N

3-to-8linedecoder,demultiplexerwithaddresslatchesinverting