3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSC

国半

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSC

国半

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or ind

文件：68.59 Kbytes 页数：8 Pages

PHI

PHI

3-to-8 line decoder, demultiplexer with address latches inverting

文件：107.6 Kbytes 页数：19 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer with address latches; inverting

文件：72.22 Kbytes 页数：8 Pages

PHI

PHI