4-bit Parallel-Access Shift Register

Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Features • High Speed Operation: tpd (Clock to Q) = 13 n

文件：189.66 Kbytes 页数：8 Pages

RENESAS

瑞萨

8 BIT PIPO SHIFT REGISTER

DESCRIPTION The M54/74HC195 is a high speed CMOS 4 BIT PIPO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 13 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：264.08 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

4-Bit Universal Shift Register High?밣erformance Silicon?밎ate CMOS

4-Bit Universal Shift Register High–Performance Silicon–Gate CMOS The MC74HC195 is identical in pinout to the LS195. The device inputs are compatible with standard CMOS outputs, with pull up resistors, they are compatible with LSTTL outputs. This static shift register features parallel load, ser

文件：206.51 Kbytes 页数：7 Pages

MOTOROLA

摩托罗拉

4-Bit Parallel Shift Register

文件：171.07 Kbytes 页数：6 Pages

NSC

国半