Triple 3-input AND Gates

Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

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HitachiHitachi Semiconductor

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Triple 3-input AND Gates

Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.37 Kbytes 页数：7 Pages

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Triple 3-input AND Gate

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Standard IC>General-Purpose Logics>HD74HC Series

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Dual J-K Flip-Flops (with Preset and Clear)

Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logi

文件：60.22 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

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Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：52.31 Kbytes 页数：8 Pages

HitachiHitachi Semiconductor

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Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：188.83 Kbytes 页数：7 Pages

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Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：188.83 Kbytes 页数：7 Pages

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瑞萨

Dual J-K Flip-Flops (with Preset)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Featu

文件：188.83 Kbytes 页数：7 Pages

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瑞萨

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are indep

文件：49 Kbytes 页数：8 Pages

HitachiHitachi Semiconductor

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