Dual J-K Flip-Flops (with Preset and Clear)

Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logi

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HitachiHitachi Semiconductor

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Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

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Dual J-K Flip-Flops (with Preset and Clear)

Description\nEach flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic le •  High Speed Operation: tpd(Clock to Q) = 17 ns typ (CL = 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 2 µA max (Ta = 25°C);

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Standard IC>General-Purpose Logics>HD74HC Series

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Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

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Dual J-K Flip-Flops (with Preset and Clear)

文件：102.89 Kbytes 页数：7 Pages

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Dual 4-bit Binary Counters

Description\nEach flip-flop has independent J, K, preset, clear and clock inputs and Q and Qoutputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic le •  High Speed Operation: tpd(Clock to Q) = 17 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 2 µA max (Ta = 25°C)\n•  Ordering Information;

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