1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

Hynix

海力士

1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

Hynix

海力士

1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

Hynix

海力士

1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士

256Mb DDR2 SDRAM

Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data S

文件：1.13655 Mbytes 页数：61 Pages

Hynix

海力士