1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

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海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

文件：1.37896 Mbytes 页数：62 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Description Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-d

文件：570.64 Kbytes 页数：44 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

HYNIX

海力士

1Gb DDR2 SDRAM

Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transacti

文件：842.79 Kbytes 页数：63 Pages

HYNIX

海力士