INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor

56F826 16-bit Hybrid Controller • Up to 40 MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Hardware DO and REP loops • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • 3

文件：591.17 Kbytes 页数：44 Pages

Motorola

摩托罗拉

Digitial Signal Controller

56853 General Description • 120 MIPS at 120MHz • 12K x 16-bit Program SRAM • 4K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M of data memory • Chip Select Logic for glue-less interface to ROM and SRAM • Six (6) independent channels of DMA • Enhan

文件：15.9841 Mbytes 页数：662 Pages

freescaleFreescale Semiconductor, Inc

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16-bit Digital Signal Controllers

56F8367/56F8167 General Description Note: Features in italics are NOT available in the 56F8167 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 4MB of off-chip program and 32MB of data memory • Chip S

文件：2.45398 Mbytes 页数：184 Pages

freescaleFreescale Semiconductor, Inc

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16-bit Digital Signal Controllers

56F8013/56F8011 Description The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power ofa DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost

文件：1.88093 Mbytes 页数：124 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

16-bit Digital Signal Controllers

56853 General Description • 120 MIPS at 120MHz • 12K x 16-bit Program SRAM • 4K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M of data memory • Chip Select Logic for glue-less interface to ROM and SRAM • Six (6) independent channels of DMA • Enhan

文件：1.55051 Mbytes 页数：60 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

16-bit Digital Signal Controllers

56854 General Description • 120 MIPS at 120MHz • 16K x 16-bit Program SRAM • 16K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program or 8M data memory • Chip Select Logic for glue-less interface to ROM and SRAM • Six (6) independent channels of DMA • Enhanced Synch

文件：1.55141 Mbytes 页数：60 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体