DSP56603EVM Evaluation Module

FEATURES • 16-bit DSP56603 Digital Signal Processor – High Performance DSP56600 Core • 60 Million Instructions Per Second (MIPS) with a 60 MHz clock (at 2.7 volts) • Object-code compatible with the DSP56000 and DSP56300 cores • Highly parallel instruction set • Fully pipelined 16 ´ 16-bit

文件：321.35 Kbytes 页数：8 Pages

恩XP

DSP56603EVM Evaluation Module

FEATURES • 16-bit DSP56603 Digital Signal Processor – High Performance DSP56600 Core • 60 Million Instructions Per Second (MIPS) with a 60 MHz clock (at 2.7 volts) • Object-code compatible with the DSP56000 and DSP56300 cores • Highly parallel instruction set • Fully pipelined 16 ´ 16-bit

文件：321.35 Kbytes 页数：8 Pages

恩XP

DSP56603EVM Evaluation Module

FEATURES • 16-bit DSP56603 Digital Signal Processor – High Performance DSP56600 Core • 60 Million Instructions Per Second (MIPS) with a 60 MHz clock (at 2.7 volts) • Object-code compatible with the DSP56000 and DSP56300 cores • Highly parallel instruction set • Fully pipelined 16 ´ 16-bit

文件：321.35 Kbytes 页数：8 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP