DSP56651

Integrated Baseband Processor Development IC; RISC M·CORE MCU\n\n•32-bit load/store RISC architecture\n•Fixed 16-bit instruction length\n•16-entry 32-bit general-purpose register file\n•32-bit internal address and data buses\n•Efficient four-stage, fully interlocked execution pipeline\n•Single-cycle execution for most instructions, two cycles for branches and memory accesses\n•Special branch, byte, and bit manipulation instructions\n•Support for byte, half-word, and word memory accesses\n•Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file\n\nHigh-performance DSP56600 core\n\n•1 x engine (e.g., 70 MHz = 70 MIPS)\n•Fully pipelined 16 x 16-bit parallel Multiplier-Accumulator (MAC)\n•Two 40-bit accumulators including extension bits\n•40-bit parallel barrel shifter\n•Highly parallel instruction set with unique DSP addressing modes\n•Position-independent code support\n•Nested hardware DO loops\n•Fast auto-return interrupts\n•On-chip support for software patching and enhancements\n•Realtime trace capability via external address bus\n\nOn-chip memories\n\n•4K x 32-bit MCU ROM\n•512 x 32-bit MCU RAM\n•24K x 24-bit DSP Program ROM\n•24K x 24-bit DSP Program RAM\n•18K x 16-bit DSP data ROM, split into 9K x 16-bit X and 9K x 16-bit Y data ROM\n•16K x 16-bit DSP data RAM, split into (7+1)K x 16-bit X and 8K x 16-bit Y data RAM\n\nOn-chip peripherals\n\n•Fully programmable Phase-locked Loop (PLL) for DSP clock generation\n•External Interface Module (EIM) for glueless system integration\n•External 22-bit address and 16-bit data MCU buses\n•Thirty-two source MCU Interrupt Controller\n•Intelligent MCU/DSP Interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control\n•Serial audio codec port\n•Serial baseband codec port\n•Protocol timer frees the MCU from radio channel timing events\n•Queued Serial Peripheral Interface (SPI)\n•Keypad port capable of scanning up to an 8 x 8 matrix keypad\n•General-purpose MCU and DSP timers\n•Pulse width modulation (PWM) output\n•Universal Asynchronous Receiver/Transmitter (UART) with FIFO\n•IEEE 1149.1-compliant boundary scan JTAG Test Access Port (TAP)\n•Integrated DSP/M·CORE On-Chip Emulation (OnCE™) module\n•DSP Address Bus Visibility mode for system development\n•ISO 7816-compatible SmartCard port\n\nOperating features\n\n•Comprehensive static and dynamic power management\n•M·CORE operating frequency: dc to 16.8 MHz at 2.4 V\n•DSP operating frequency: dc to 58.8 MHz at 2.4 V\n•Operating temperature: -40° to 85°C ambient\n•Package option: 17 x 17 mm, 196-lead PBGA\n;

Overview The DSP56651 has been placed on \"NotRecommended for New Designs\" status. This is NOTan End-of-Life Notice. \n The RAM-based DSP56651 emulation device is designedto support the rigorous demands of developingapplications for the cellular subscriber market.The high level of on-chip integration in theDSP56651 and its volume production companiondevice DSP56652 minimizes application systemdesign complexity and component count, resultingin very compact implementations. \n

DSP56651

INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

DSP56651D

INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC