DSP56800EERM中文资料飞思卡尔数据手册PDF规格书

56F8367/56F8167 General Description

Note: Features in italics are NOT available in the 56F8167 device.

• Up to 60 MIPS at 60MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• Access up to 4MB of off-chip program and 32MB of data memory

• Chip Select Logic for glueless interface to ROM and SRAM

• 512KB of Program Flash

• 4KB of Program RAM

• 32KB of Data Flash

• 32KB of Data RAM

• 32KB Boot Flash

• Up to two 6-channel PWM modules

• Four 4-channel, 12-bit ADCs

• Temperature Sensor

• Up to two Quadrature Decoders

• Optional on-chip regulator

• Up to two FlexCAN modules

• Two Serial Communication Interfaces (SCIs)

• Up to two Serial Peripheral Interfaces (SPIs)

• Up to four general-purpose Quad Timers

• Computer Operating Properly (COP) / Watchdog

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 76 GPIO lines

• 160-pin LQFP Package and 160 MAPBGA

56F8367/56F8167 Features

Core

• Efficient 16-bit 56800E family controller engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set withunique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface

Memory

Note: Features in italics are NOT available in the 56F8167 device.

• Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security protection feature

• On-chip memory, including a low-cost, high-volume Flash solution

— 512KB of Program Flash

— 4KB of Program RAM

— 32KB of Data Flash

— 32KB of Data RAM

— 32KB of Boot Flash

• Off-chip memory expansion capabilities provide a simple method for interfacing additional external memory and/or peripheral devices

— Access up to 4MB of external program memory or 32MB of external data memory

— Chip select logic for glueless interface to ROM and SRAM

• EEPROM emulation capability