DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

文件：246.29 Kbytes 页数：8 Pages

恩XP

DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

文件：246.29 Kbytes 页数：8 Pages

恩XP

DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

文件：246.29 Kbytes 页数：8 Pages

恩XP

DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

文件：246.29 Kbytes 页数：8 Pages

恩XP

24-BIT DIGITAL SIGNAL PROCESSOR

FEATURES High-Performance DSP56300 Core ¥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O ¥ Object code compatible with the DSP56000 core ¥ Highly parallel instruction set ¥ Data arithmetic logic unit (ALU) Ð Fully pipelined 24 x 24-bit parallel m

文件：1.83703 Mbytes 页数：156 Pages

恩XP

24-BIT DIGITAL SIGNAL PROCESSOR

24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in

文件：947.84 Kbytes 页数：156 Pages

Motorola

摩托罗拉

24-BIT DIGITAL SIGNAL PROCESSOR

24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in

文件：947.84 Kbytes 页数：156 Pages

Motorola

摩托罗拉

DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

文件：246.29 Kbytes 页数：8 Pages

恩XP

24-BIT DIGITAL SIGNAL PROCESSOR

FEATURES High-Performance DSP56300 Core ¥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O ¥ Object code compatible with the DSP56000 core ¥ Highly parallel instruction set ¥ Data arithmetic logic unit (ALU) Ð Fully pipelined 24 x 24-bit parallel m

文件：1.83703 Mbytes 页数：156 Pages

恩XP

24-BIT DIGITAL SIGNAL PROCESSOR

FEATURES High-Performance DSP56300 Core ¥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O ¥ Object code compatible with the DSP56000 core ¥ Highly parallel instruction set ¥ Data arithmetic logic unit (ALU) Ð Fully pipelined 24 x 24-bit parallel m

文件：1.83703 Mbytes 页数：156 Pages

恩XP