18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM 4-Word Burst Architecture

文件：1.20946 Mbytes 页数：29 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

文件：695.1 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司