CY7C1313CV18集成电路（IC）的存储器规格书PDF中文资料

CY7C1313CV18属于集成电路（IC）的存储器。由赛普拉斯半导体公司制造生产的CY7C1313CV18存储器存储器是集成电路上用作数据存储设备的半导体器件。这些器件分为非易失性或易失性两种，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、闪存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。这些器件的存储容量为 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、单线、SPI、UFS、Xccela 总线和 1-线。

Functional Description

The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

特性 Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II operates with 1.5 cycle read latency when the Delay

Lock Loop (DLL) is enabled

■ Operates as a QDR-I device with 1 cycle read latency in DLL

off mode

■ Available in x 8, x 9, x 18, and x 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement