CDCE6214中文资料Ultra-low power clock generator with one PLL, four differential output数据手册TI规格书

描述 Description

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

特性 Features

• Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout > 100 MHz) as:
• Differential output: 350 fs typical, 600 fs maximum
• Fractional mode:
• LVCMOS output: 2.0 ps typical, 4.0 ps maximum
• Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
• Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
• Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
• Flexible output clock distribution
• Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
• Individual output enable through GPIO and register
• Frequency margining options
• Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
• Configurable GPIOs and flexible configuration options
• Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
• Supports 100-Ω systems
• Small footprint: 24-pin VQFN (4 mm × 4 mm)