CDCDB400中文资料4-output clock buffer for PCIe® Gen 1 to Gen 5数据手册TI规格书

描述 Description

The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.

特性 Features

• 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
• Additive phase jitter after PCIE Gen5 filter:
• Programmable output slew rate control
• 3.3-V core and IO supply voltages
• Current consumption: 46 mA maximum
• 5-mm × 5-mm, 32-pin VQFN package