CDCDB400数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.

特性 Features

• 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
• 4 hardware output enable (OE#) controls
• Additive phase jitter after PCIE Gen5 filter:
• Output-to-output skew: Fail-safe input
• Programmable output slew rate control
• 3 selectable SMBus addresses
• 3.3-V core and IO supply voltages
• Hardware-controlled low power mode (PD#)
• Current consumption: 46 mA maximum
• 5-mm × 5-mm, 32-pin VQFN package