CDCDB400中文资料4-output clock buffer for PCIe® Gen 1 to Gen 5数据手册TI规格书

描述 Description

The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.

特性 Features

• 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
• Additive phase jitter after PCIE Gen5 filter:
• Programmable output slew rate control
• 3.3-V core and IO supply voltages
• Current consumption: 46 mA maximum
• 5-mm × 5-mm, 32-pin VQFN package

简介

CDCDB400属于集成电路（IC）的时钟缓冲器驱动器。由TI制造生产的CDCDB400时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。