NCV809SN293D1T1G

Marking：ACT；Package：SOT23-3；Very Low Supply Current 3-Pin Microprocessor Reset Monitors

SMAJ43A

Marking：ACT；Package：SMA；Transient Voltage Suppressor

SMB10J43CA

Marking：ACT；Package：DO-214AA；Surface Mount Transient Voltage Suppressors

74ACT11008D

Marking：ACT11008；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-AND GATE

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurations MinimizeHigh-SpeedSwitchingNoise EPICE(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D),PlasticThinShrink Small-Outli

74ACT11008D.A

Marking：ACT11008；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-AND GATE

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurations MinimizeHigh-SpeedSwitchingNoise EPICE(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D),PlasticThinShrink Small-Outli

74ACT11032D

Marking：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunityat125°C PackageOptionsIncludePlastic Small-OutlinePackages(D),PlasticShrink Small

74ACT11032DR

Marking：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunityat125°C PackageOptionsIncludePlastic Small-OutlinePackages(D),PlasticShrink Small

74ACT11032DR.A

Marking：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunityat125°C PackageOptionsIncludePlastic Small-OutlinePackages(D),PlasticShrink Small

74ACT11074D

Marking：ACT11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D)andShrinkSmall-Outline (DB)

74ACT11074D.A

Marking：ACT11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D)andShrinkSmall-Outline (DB)