丝印：ACT10；Package：SOIC(D)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

TI

德州仪器

丝印：ACT10；Package：SOIC(D)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

TI

德州仪器

丝印：ACT10；Package：SOIC(D)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

TI

德州仪器

丝印：ACT10；Package：SOIC(D)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

TI

德州仪器

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器