丝印：ACT1284；Package：SOIC；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

丝印：ACT1284；Package：SOIC；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

丝印：ACT1284；Package：SOIC；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

丝印：ACT1284；Package：SOIC；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

丝印：ACT1284；Package：SOP；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

丝印：ACT1284；Package：SOP；7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 20 ns at 5 V 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds JESD 22 − 2000-V Hu

文件：888.17 Kbytes 页数：21 Pages

TI

德州仪器

7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

文件：287.26 Kbytes 页数：12 Pages

TI

德州仪器