74ACT11074NSR

Marking：ACT11074；Package：SOP；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D)andShrinkSmall-Outline (DB)

74ACT11074NSR.A

Marking：ACT11074；Package：SOP；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-
mProcess 500-mATypicalLatch-UpImmunity at125°C PackageOptionsIncludePlastic Small-Outline(D)andShrinkSmall-Outline (DB)

74ACT11139D

Marking：ACT11139；Package：SOIC；DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

InputsAreTTL-VoltageCompatible DesignedSpecificallyforHigh-Speed MemoryDecodersandDataTransmission Systems IncorporatesTwoEnableInputstoSimplify Cascadingand/orDataReception FullySynchronousOperationforCounting Center-PinVCCandGNDConfigurations MinimizeHigh-Speed

74ACT11139D.A

Marking：ACT11139；Package：SOIC；DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

InputsAreTTL-VoltageCompatible DesignedSpecificallyforHigh-Speed MemoryDecodersandDataTransmission Systems IncorporatesTwoEnableInputstoSimplify Cascadingand/orDataReception FullySynchronousOperationforCounting Center-PinVCCandGNDConfigurations MinimizeHigh-Speed

74ACT11240DW

Marking：ACT11240；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

InputsAreTTL-VoltageCompatible Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurations MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mATypicalLatch-UpImmunityat 125°C PackageOptionsIncludePlastic Sm

74ACT11240DW.A

Marking：ACT11240；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

InputsAreTTL-VoltageCompatible Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurations MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mATypicalLatch-UpImmunityat 125°C PackageOptionsIncludePlastic Sm

74ACT11244DW

Marking：ACT11244；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

3-StateOutputsDriveBusLinesorBuffer MemoryAddressRegisters InputsAreTTL-VoltageCompatible Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mA

74ACT11244DWR

Marking：ACT11244；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

3-StateOutputsDriveBusLinesorBuffer MemoryAddressRegisters InputsAreTTL-VoltageCompatible Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mA

74ACT11244DWR.A

Marking：ACT11244；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

3-StateOutputsDriveBusLinesorBuffer MemoryAddressRegisters InputsAreTTL-VoltageCompatible Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurationsto MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mA

74ACT11257DW

Marking：ACT11257；Package：SOIC；QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS

InputsAreTTL-VoltageCompatible 3-StateOutputsInterfaceDirectlyWith SystemBus Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDConfigurations MinimizeHigh-SpeedSwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-mProcess 500-mATypicalLatch-UpIm