16-bit D-type registered transceiver; 3-state

DESCRIPTION The 74ALVCH16543 is a dual octal registered transceiver. FEATURES • In accordance with JEDEC standard no 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE flow-through pin-out architecture • 16-bit transceiver with D-type latch • Combines 16

文件：89.86 Kbytes 页数：20 Pages

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16-bit bus transceiver/register 3-State

DESCRIPTION The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low

文件：92.33 Kbytes 页数：12 Pages

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16-bit transceiver/register with dual enable; 3-state

DESCRIPTION The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. FEATURES • In accordance with JE

文件：103.23 Kbytes 页数：20 Pages

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20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

文件：95.31 Kbytes 页数：12 Pages

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20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

文件：95.31 Kbytes 页数：12 Pages

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18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

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18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

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18-bit buffer/driver 3-State

DESCRIPTION The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with 3-State outputs for bus-oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Curr

文件：73.48 Kbytes 页数：10 Pages

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20-bit buffer/line driver, non-inverting 3-State

DESCRIPTION The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-State outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Wide supply voltage range of 1.2V to 3.6V • CMOS low power consumption • Di

文件：72.51 Kbytes 页数：10 Pages

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20-bit bus interface D-type latch 3-State

DESCRIPTION The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. FEATUR

文件：77.81 Kbytes 页数：10 Pages

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