ACH16821DL中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A

• Current drive ± 24 mA at 3.0 V

• CMOS low power consumption

• Direct interface with TTL levels

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and ground pins for minimum noise and ground bounce

• All data inputs have bus hold

• Output drive capability 50Ω transmission lines @ 85°C