4-Output 3.3V HCSL PCIe Buffer

Description The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1–3 in zero delay mode and PCIe Gen1–4 in fanout mode. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434 with a Safe-Power-Sequence (SPS) clock input. Features ▪ SPS internal

文件：398.36 Kbytes 页数：18 Pages

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Six Output Differential Buffer for PCIe Gen3

General Description: The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the inp

文件：332.75 Kbytes 页数：15 Pages

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Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

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Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

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瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨

Six Output Differential Buffer for PCIe Gen3

Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused out

文件：298.62 Kbytes 页数：15 Pages

RENESAS

瑞萨