EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

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瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

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8-Output 3.3V HCSL PCIe Buffer

Description The 9DB836 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1–3 in zero-delay mode and PCIe Gen1–4 in fanout mode. The 9DB836 is a pin-compatible upgrade to the 9DB833 and 9DB834 with a Safe Power Sequence (SPS) clock input. Features ▪ SPS internal

文件：618.41 Kbytes 页数：21 Pages

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

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