9DB836中文资料瑞萨数据手册PDF规格书

描述 Description

The 9DB836 is a zero delay/fanout buffer for PCI Express™

clocking. It supports PCIe Gen1–3 in zero-delay mode and PCIe

Gen1–4 in fanout mode. The 9DB836 is a pin-compatible upgrade

to the 9DB833 and 9DB834 with a Safe Power Sequence (SPS)

clock input.

特性 Features

▪ SPS internal receiver bias network keeps input clock parked

when input is floating

▪ Supports both 85Ω and 100Ω output impedance with

appropriate resistor selection

▪ OE# pins default to controlling outputs

▪ PLL or Bypass mode; PLL can dejitter incoming clock

▪ Selectable PLL bandwidth; minimizes jitter peaking in

downstream PLLs

▪ Spread spectrum compatible

▪ Outputs default to Hi-Z when disabled or when device is

powered down

▪ SMBus interface; unused outputs can be disabled

▪ 3 selectable SMBus addresses