丝印：9DB；Package：SOT-23；PNP Epitaxial Silicon Transistor

Features • Switching and Amplifier Applications • Suitable for automatic insertion in thick and thin-film circuits • Low Noise: BC859, BC860 • Complement to BC846 BC850

文件：150.03 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

文件：301.33 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

• CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/

文件：267.2 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

• CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/

文件：267.2 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

文件：301.33 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

文件：301.33 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

• CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/

文件：267.2 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

• CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/

文件：267.2 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

文件：301.33 Kbytes 页数：14 Pages

RENESAS

瑞萨

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

文件：301.33 Kbytes 页数：14 Pages

RENESAS

瑞萨