2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

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瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

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瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 and 4-Output 3.3V PCIe Gen1–7 Clock Fanout Buffers with LOS

▪ FPS: VDD may be applied with floating input clock, or input clock may be driven before VDD is applied ▪ ACP: Outputs automatically park low/low when LOS occurs and cleanly start when LOS is removed ▪ PDT: Input pins may be driven before VDD is applied and will not damage the device ▪ 2 or

文件：747.66 Kbytes 页数：16 Pages

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2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean

文件：805.18 Kbytes 页数：17 Pages

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瑞萨

2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean

文件：805.18 Kbytes 页数：17 Pages

RENESAS

瑞萨

2 and 4-Output 3.3V PCIe Gen1–7 Clock Fanout Buffers with LOS

▪ FPS: VDD may be applied with floating input clock, or input clock may be driven before VDD is applied ▪ ACP: Outputs automatically park low/low when LOS occurs and cleanly start when LOS is removed ▪ PDT: Input pins may be driven before VDD is applied and will not damage the device ▪ 2 or

文件：747.66 Kbytes 页数：16 Pages

RENESAS

瑞萨