Cisco Catalyst 9130AX Series Access Points

Wi-Fi 6 (802.11ax) The IEEE 802.11ax emerging standard, also known as High-Efficiency Wireless (HEW) or Wi-Fi 6, builds on 802.11ac. It delivers a better experience in typical environments with more predictable performance for advanced applications such as 4K or 8K video, high-density, high-defin

文件：1.16978 Mbytes 页数：17 Pages

CISCO

思科

类别：测试与计量 设备 - 电源（测试，工作台） 描述：PWR SUPPLY DC TRIPLE OUTPUT PROG

B\u0026K Precision

类别：测试与计量 设备 - 电源（测试，工作台） 描述：PWR SUPPLY DC TRIPLE OUTPUT PROG

B\u0026K Precision

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

文件：163.27 Kbytes 页数：9 Pages

IDT

丝印：305IL；Package：TSSOP；HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

文件：335.12 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：305IL；Package：TSSOP；HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

文件：335.12 Kbytes 页数：10 Pages

RENESAS

瑞萨

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

文件：163.27 Kbytes 页数：9 Pages

IDT

丝印：305AMILF；Package：SOIC；HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

文件：335.12 Kbytes 页数：10 Pages

RENESAS

瑞萨

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

文件：163.27 Kbytes 页数：9 Pages

IDT

丝印：305AMILF；Package：SOIC；HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

文件：335.12 Kbytes 页数：10 Pages

RENESAS

瑞萨