91305AGILF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.

特性 Features

• Zero input - output delay

• Frequency range 10 - 133 MHz (3.3V)

• 5V tolerant input REF

• High loop filter bandwidth ideal for Spread Spectrum applications

• Less than 200 ps Jitter between outputs

• Skew controlled outputs

• Skew less than 250 ps between outputs

• Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages

• 3.3V ±10 operation

• Supports industrial temperature range -40°C to 85°C