HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

文件：163.27 Kbytes 页数：9 Pages

IDT

丝印：305IL；Package：TSSOP；HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

文件：335.12 Kbytes 页数：10 Pages

RENESAS

瑞萨

Package：8-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK DRIVER LO JITTER 8TSSOP

RENESAS

瑞萨

High Performance Communication Buffer

General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s

文件：86.61 Kbytes 页数：8 Pages

ICST

High Performance Communication Buffer

General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s

文件：86.61 Kbytes 页数：8 Pages

ICST

32-bit Microcontroller

文件：880.72 Kbytes 页数：90 Pages

FUJITSU

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