Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

文件：478.94 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：870919BRI-01L；Package：QSOP；LVCMOS Clock Generator

Features • Two selectable single-ended input reference clocks • Eight single-ended clock outputs • Internal PLL does not require external loop filter components • 5V tolerant inputs • Maximum output frequency: 160MHz, (2XQ output) • Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs) •

文件：378.89 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：870919BRI-01L；Package：QSOP；LVCMOS Clock Generator

Features • Two selectable single-ended input reference clocks • Eight single-ended clock outputs • Internal PLL does not require external loop filter components • 5V tolerant inputs • Maximum output frequency: 160MHz, (2XQ output) • Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs) •

文件：378.89 Kbytes 页数：16 Pages

RENESAS

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