Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

文件：478.94 Kbytes 页数：19 Pages

RENESAS

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Output frequency range

文件：276.24 Kbytes 页数：18 Pages

IDT

Zero Delay, Differential-to-LVCMOS/LVTTL Clock Generator

The 8705I is a highly versatile 1:8 Differential-to- LVCMOS/LVTTL Clock Generator. The 8705I has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The 8705I has a fully integrated PLL ·Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance\n·Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs\n·CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·CLK0 input accepts LVCMOS or LVTTL input levels\n·Output frequency range: 15.625MHz;

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6-bit high-speed dual Analog-to-Digital Converter ADC

文件：117.56 Kbytes 页数：16 Pages

PHI

PHI

6-bit high-speed dual Analog-to-Digital Converter ADC

文件：111 Kbytes 页数：16 Pages

PHI

PHI

6-bit high-speed dual Analog-to-Digital Converter ADC

文件：117.56 Kbytes 页数：16 Pages

PHI

PHI