Triple buffer gate

General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5

文件：79.74 Kbytes 页数：14 Pages

PHI

飞利浦

TRIPLE BUFFER GATE

Features  Wide Supply Voltage Range from 1.65V to 5.5V  ±24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs Accept up to 5.5V  ESD Protection Tested per JESD 22 Exceeds 2,000V Human Body Model (A114) Exceeds 1,000V Charged D

文件：470.83 Kbytes 页数：8 Pages

DIODES

美台半导体

Triple buffer

General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF.

文件：87.32 Kbytes 页数：14 Pages

恩XP

Triple buffer

1. General description The 74LVC3G34 is a triple buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise a

文件：258.839 Kbytes 页数：16 Pages

NEXPERIA

安世

Triple buffer

文件：100.65 Kbytes 页数：16 Pages

恩XP

Triple gate 1 Input Buffer

The DIODES™ 74LVC3G34 is a triple buffer gate with standard push-pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial po

Diodes

美台半导体

丝印：V34；Package：SOT765-1；Triple buffer

1. General description The 74LVC3G34 is a triple buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise a

文件：258.839 Kbytes 页数：16 Pages

NEXPERIA

安世

Triple buffer

General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF.

文件：87.32 Kbytes 页数：14 Pages

恩XP

Triple buffer gate

General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5

文件：79.74 Kbytes 页数：14 Pages

PHI

飞利浦

Triple buffer gate

General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5

文件：79.74 Kbytes 页数：14 Pages

PHI

飞利浦