首页 >74LVC3G34DC>规格书列表
| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
74LVC3G34DC | Triple buffer gate General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 文件:79.74 Kbytes 页数:14 Pages | PHI 飞利浦 | PHI | |
74LVC3G34DC | Triple buffer General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. 文件:87.32 Kbytes 页数:14 Pages | 恩XP | 恩XP | |
74LVC3G34DC | 丝印:V34;Package:SOT765-1;Triple buffer 1. General description The 74LVC3G34 is a triple buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise a 文件:258.839 Kbytes 页数:16 Pages | NEXPERIA 安世 | NEXPERIA | |
74LVC3G34DC | Triple buffer 文件:100.65 Kbytes 页数:16 Pages | 恩XP | 恩XP | |
丝印:Y34;Package:VSSOP8;Triple buffer 文件:200.19 Kbytes 页数:11 Pages | NEXPERIA 安世 | NEXPERIA | ||
74LVC3G34DC | Triple buffer The 74LVC3G34 provides three buffers.\n Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the ou • Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant input/output for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceed; | Nexperia 安世 | Nexperia | |
Triple buffer The 74LVC3G34-Q100 provides three buffers.\n The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34-Q100 as a translator in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The I • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant input/output for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:; | Nexperia 安世 | Nexperia | ||
Package:8-VFSOP(0.091",2.30mm 宽);包装:管件 类别:集成电路(IC) 缓冲器,驱动器,接收器,收发器 描述:IC BUF NON-INVERT 5.5V 8VSSOP | Nexperia USA Inc. | Nexperia USA Inc. | ||
Package:8-VFSOP(0.091",2.30mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 缓冲器,驱动器,接收器,收发器 描述:IC BUF NON-INVERT 5.5V 8VSSOP | Nexperia USA Inc. | Nexperia USA Inc. |
技术参数
- VCC (V):
1.65 - 5.5
- Logic switching levels:
CMOS/LVTTL
- Output drive capability (mA):
± 32
- fmax (MHz):
175
- Nr of bits:
3
- Power dissipation considerations:
low
- Tamb (°C):
-40~125
- Rth(j-a) (K/W):
205
- Rth(j-c) (K/W):
115
- Package name:
VSSOP8
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
24+ |
标准封装 |
10048 |
全新原装正品/价格优惠/质量保障 |
询价 | ||
恩XP |
1549+ |
NA |
9000 |
询价 | |||
恩XP |
2024+ |
N/A |
70000 |
柒号只做原装 现货价秒杀全网 |
询价 | ||
恩XP |
24+ |
N/A |
16448 |
原厂可订货,技术支持,直接渠道。可签保供合同 |
询价 | ||
恩XP |
1549+ |
NA |
9000 |
询价 | |||
恩XP |
23+ |
N/A |
12000 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
PHI |
24+ |
8PIN |
3000 |
原装现货假一罚十 |
询价 | ||
PHI |
23+ |
NA |
1887 |
专做原装正品,假一罚百! |
询价 | ||
恩XP |
25+23+ |
VSSOP8 |
52481 |
绝对原装正品现货,全新深圳原装进口现货 |
询价 | ||
恩XP |
1549/+ |
NA |
12000 |
原装正品现货,可开发票,假一赔十 |
询价 |
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