Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

文件：87.2 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

文件：259.62 Kbytes 页数：14 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

文件：259.62 Kbytes 页数：14 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

文件：259.62 Kbytes 页数：14 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

文件：259.62 Kbytes 页数：14 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

PHI