Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

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PHI

飞利浦

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

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NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

文件：95.73 Kbytes 页数：10 Pages

PHI

飞利浦

Octal D-type flip-flop with reset; positive-edge trigger

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NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transfer • Wide supply voltage range from 1.2 to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at +85 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V;

Nexperia

安世

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transfer • Wide supply voltage range from 1.2 to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at +85 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V;

Nexperia

安世

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273-Q100 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is tra • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.2 V to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output dr;

Nexperia

安世

Package：20-SOIC（0.295"，7.50mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SO

Nexperia USA Inc.

Package：20-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.

Package：20-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.