Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

文件：86.38 Kbytes 页数：15 Pages

PHI

PHI

SINGLE 2 INPUT POSITIVE NAND GATE

Description The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is full

文件：199.81 Kbytes 页数：11 Pages

DIODES

美台半导体

Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

SINGLE 2-INPUT NAND GATE

Features * Operate fom 165V 10 5 5v « Inputs accept voltages to 5.57 * High Noise Immunity * Low power dissipation * ESD Protection Exceeds JESD 22 = 2000-V Human-Body Model (A114-A) ~ 1000-V Charged-Device Model (C101) * SOT23-5 Package Available + SOT353 Package Available

文件：1.98953 Mbytes 页数：6 Pages

TECHPUBLIC

台舟电子

丝印：VA；Package：SOT-891；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：VA；Package：SOT-886；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：VA；Package：SOT-886；Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

文件：86.38 Kbytes 页数：15 Pages

PHI

PHI

丝印：VA；Package：SOT886；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：VA；Package：SOT1115；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世