3-Line to 8-Line Inverting Decoder/Demultiplexer

The 74LVC138 is a 3-line to 8-line decoder/demultiplexer designed for memory address decoding or data routing applications. 0A, 1A and 2A are three binary address inputs that determine which of the eight normally high outputs (0Y to 7Y) of the device will in low-state. 1E and 2E are two active low e • Wide Supply Voltage Range: 1.2V to 3.6V\n\n• Inputs Accept Voltages up to 5V with 5V Logic\n\n• Mutually Exclusive Outputs\n\n• Multiple Input Enable in favor of Expansion\n\n• Operate as a Demultiplexer\n\n• Memory Selector\n\n• CMOS Low Power Dissipation\n\n• Inputs are Compatible with TTL Level;

SGMICRO

圣邦股份

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

文件：258.69 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

文件：258.69 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

文件：258.69 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

文件：258.69 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI