74LVC138中文资料3-Line to 8-Line Inverting Decoder/Demultiplexer数据手册SGMICRO规格书

描述 Description

The 74LVC138 is a 3-line to 8-line decoder/demultiplexer designed for memory address decoding or data routing applications. 0A, 1A and 2A are three binary address inputs that determine which of the eight normally high outputs (0Y to 7Y) of the device will in low-state. 1E and 2E are two active low enable inputs and 3E is an active high enable input. All the outputs are in a high-state except the case that 1E and 2E are low and 3E is high. The output is enabled only when all 1E, 2E and 3E are active.
This device also features the multiple input enable function for easy parallel expansion. Just four 74LVC138 devices and one inverter can make up a 1-of-32 (5-line to 32-line) decoder. When it operates as an eight-output demultiplexer, one of the active low enable inputs is used as data input and the remaining enable inputs are used as strobes. The unused enable inputs should be tied to high or low.

特性 Features

• Wide Supply Voltage Range: 1.2V to 3.6V

• Inputs Accept Voltages up to 5V with 5V Logic

• Mutually Exclusive Outputs

• Multiple Input Enable in favor of Expansion

• Operate as a Demultiplexer

• Memory Selector

• CMOS Low Power Dissipation

• Inputs are Compatible with TTL Levels

• Output Drive Capability: 50Ω Transmission Lines at +125℃

• -40℃ to +125℃ Operating Temperature Range

• Functional Operation from -10℃ to +85℃ at VCC = 1.14V

• Available in Green TQFN-2.5×3.5-16L, SOIC-16 and TSSOP-16 Packages