3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

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PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

文件：258.69 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

文件：94.61 Kbytes 页数：10 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

文件：245.96 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.\n There are three enable inputs: two active LOW (E1 and E2) and one active HIGH • 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory chip select decoding\n• Mutually exclusiv;

Nexperia

安世

3-to-8 line decoder/demultiplexer; inverting

The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.\n There are three enable inputs: two active LOW (E1 and E2) and one active HIGH • 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory chip select decoding\n• Mutually exclusiv;

Nexperia

安世

3-to-8 line decoder/demultiplexer; inverting

The 74LVC138A-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2). When the inputs are enabled, it provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.\n There are three enable inputs: two active LOW (E1 and E2) • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL lev;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1 X 3:8 16SO

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1X3:8 16SSOP

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1X3:8 16SSOP

Nexperia USA Inc.