Triple 3-input NAND gate

DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standar

文件：108.29 Kbytes 页数：8 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Triple 3-input NAND gate

1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits • Wide supply voltage range from 1.2 V to

文件：233.29 Kbytes 页数：12 Pages

NEXPERIA

安世

Triple 3-input NAND gate

DESCRIPTION The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard n

文件：84.61 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits • Wide supply voltage range from 1.2 V to

文件：233.29 Kbytes 页数：12 Pages

NEXPERIA

安世

Triple 3-input NAND gate

1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits • Wide supply voltage range from 1.2 V to

文件：233.29 Kbytes 页数：12 Pages

NEXPERIA

安世